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2-Phase Stepper-Motor Driver
TLE 4729 G
Overview Features * 2 x 0.7 amp. full bridge outputs * Integrated driver, control logic and current control (chopper) * Very low current consumption in inhibit mode * Fast free-wheeling diodes * Max. supply voltage 45 V * Output stages are free of crossover current * Offset-phase turn-ON of output stages * All outputs short-circuit proof * Error-flag for overload, open load, over-temperature * SMD package P-DSO-24-3 Type TLE 4729 G Description Ordering Code on request
Bipolar-IC
P-DSO-24-3
Package P-DSO-24-3
TLE 4729 G is a bipolar, monolithic IC for driving bipolar stepper motors, DC motors and other inductive loads that operate by constant current. It is fully pin and function compatible except the current programing is inverse to the TLE 4728 G with an additional inhibit feature. The control logic and power output stages for two bipolar windings are integrated on a single chip which permits switched current control of motors with 0.7 A per phase at operating voltages up to 16 V. The direction and value of current are programmable for each phase via separate control inputs. In the case of low at all four current program inputs the device is switched in inhibit mode automatically. A common oscillator generates the timing for the current control and turn-on with phase offset of the two output stages. The two output stages in full-bridge configuration include fast integrated freewheeling diodes and are free of crossover current. The device can be driven directly by a microprocessor in several modes by programming phase direction and current control of each bridge independently. With the two error outputs the TLE 4729 G signals malfunction of the device. Setting the control inputs high resets the error flag and by reactivating the bridges one by one the location of the error can be found.
Semiconductor Group 1 1998-02-01
TLE 4729 G
TLE 4729 G
10 11 Phase 1 OSC GND GND GND GND Q11 R1 +V S Q12
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
20 21 Phase 2 Error 1 GND GND GND GND Q21 R2 Error 2 Q22
AEP02195
Figure 1
Pin Configuration (top view)
Semiconductor Group
2
1998-02-01
TLE 4729 G
Pin Definitions and Functions Pin No. 1, 2, 23, 24 Function Digital control inputs IX0, IX1 for the magnitude of the current of the particular phase.
Iset = 450 mA with Rsense = 1
IX1 L L H H
1)
IX0 L H L H
Phase Current Example of Motor Status 0 0.155 x Iset No current 1) Hold Normal mode Accelerate
Iset
1.55 x Iset
"No current" in both bridges inhibits the circuit and current consumption will sink below 50 A (inhibit-mode)
3
Input phase 1; controls the current through phase winding 1. On H-potential the phase current flows from Q11 to Q12, on L-potential in the reverse direction. Ground; all pins are connected at leadframe internally. Oscillator; works at approx. 25 kHz if this pin is wired to ground across 2.2 nF. Resistor R1 for sensing the current in phase 1. Push-pull outputs Q11, Q12 for phase 1 with integrated free-wheeling diodes. Supply voltage; block to ground, as close as possible to the IC, with a stable electrolytic capacitor of at least 47 F in parallel with a ceramic capacitor of 100 nF. Error 2 output; signals with "low" the errors: short circuit to ground of one or more outputs or over-temperature. Push-pull outputs Q22, Q21 for phase 2 with integrated free-wheeling diodes. Resistor R2 for sensing the current in phase 2.
5 ... 8, 17 ... 20 4 10 9, 12 11
14 13, 16 15
Semiconductor Group
3
1998-02-01
TLE 4729 G
Pin Definitions and Functions (cont'd) Pin No. 21 Function Error 1 output; signals with "low" the errors: open load or short circuit to + VS of one or more outputs or short circuit of the load or overtemperature. Input phase 2; controls the current flow through phase winding 2. On H-potential the phase current flows from Q21 to Q22, on L-potential in the reverse direction.
22
+V S OSC Oscillator T11 T12 Q11
C OSC
D11
D12 Q12
10 11
Phase 1 Error 1
Function Logic Phase 1
T13 D13 D14
T14
R1 R sense
TLE 4729 G
Error 2
Error-Flag Generation
+V S
Inhibit T21 D21 D22 Q22 T22 Q21
20 21
Phase 2
Function Logic Phase 2
T23 D23 D24
T24
R2
GND
R sense
AEB02196
Figure 2
Block Diagram
Semiconductor Group
4
1998-02-01
TLE 4729 G
Absolute Maximum Ratings Tj = - 40 to 150 C Parameter Supply voltage Error outputs Output current Ground current Logic inputs Oscillator voltage Symbol Limit Values min. max. 45 45 3 1 - 15 6 5 150 125 125 75 50 V V mA A A V V V C C C - - - - - IXX; Phase 1, 2 - - Max. 1.000 h - - 0.3 - 0.3 - -1 -2 - 15 - 0.3 - 0.3 - - 50 - - Unit Remarks
R1, R2 input voltage
Junction temperature Storage temperature Thermal resistances Junction-ambient Junction-ambient (soldered on a 35 m thick 20 cm2 PC board copper area) Junction-case
VS VErr IErr IQ IGND VIXX VOSC VRX Tj Tstg Rth ja Rth ja
K/W - K/W -
Rth jc
-
15
K/W Measured on pin 5
Operating Range Supply voltage Case temperature Output current Logic inputs Error outputs
VS TC IQ VIXX VErr IErr
5 - 40 - 800 -5 - 0
16 110 800 6 25 1
V C mA V V mA
- Measured on pin 5; Pdiss = 2 W - IXX; Phase 1, 2 - -
Semiconductor Group
5
1998-02-01
TLE 4729 G
Characteristics
VS = 6 to 16 V; Tj = - 40 to 130 C
Parameter Symbol Limit Values min. Current Consumption From + VS From + VS Oscillator Output charging current Charging threshold Discharging threshold Frequency typ. max. Unit Test Condition
IS IS
- 20
- 30
50 50
A mA
IXX = L; VS = 12; Tj 85 C IQ1, 2 = 0 A
IOSC VOSCL VOSCH fOSC
90 0.8 1.7 18
120 1.3 2.3 24
135 1.9 2.9 30
A V V kHz
- - -
COSC = 2.2 nF
Phase Current (VS = 9 ... 16 V) Mode "no current" Voltage threshold of current Comparator at Rsense in mode: Hold Setpoint Accelerate Logic Inputs (Phase X) Threshold Hysteresis L-input current L-input current H-input current
IQ Vch Vcs Vca
-
0
-
mA
IX0 = L; IX1 = L
40 410 630
70 450 700
100 510 800
mV mV mV
IX0 = H; IX1 = L IX0 = L; IX1 = H IX0 = H; IX1 = H
VI VIHy IIL IIL IIH
1.2 - - 10 - 100 -1
1.7 200 -1 - 20 0
2.2 - 1 -5 10
V mV A A A
- -
VI = 1.2 V VI = 0 V VI = 5 V
Semiconductor Group
6
1998-02-01
TLE 4729 G
Characteristics (cont'd)
VS = 6 to 16 V; Tj = - 40 to 130 C
Parameter Symbol Limit Values min. Logic Inputs (IX1; IX0) Threshold Hysteresis L-input current H-input current Error Outputs Saturation voltage Leakage current Thermal Protection Shutdown Prealarm Delta Hysteresis shutdown Hysteresis prealarm typ. max. Unit Test Condition
VI VIHy IIL IIH
0.8 - - 100 5
1.7 200 - 20
2.2 - 5 50
V mV A A
- -
VI = 0 V VI = 5 V
VErrSat IErrL
50 -
200 -
500 10
mV A
IErr = 1 mA VErr = 25 V
Tjsd Tjpa
Tj
Tjsdhy Tjpahy
140 120 10 - -
150 130 20 20 20
160 140 30 - -
C C K K K
IQ1, 2 = 0 A VErr = L Tj = Tjsd - Tjpa
- -
Power Outputs Diode Transistor Sink Pair (D13, T13; D14, T14; D23, T23; D24, T24) Saturation voltage Saturation voltage Reverse current Forward voltage Forward voltage
VsatI VsatI IRI VFI VFI
0.1 0.2 500 0.6 0.7
0.3 0.5 1000 0.9 1
0.5 0.8 1500 1.2 1.3
V V A V V
IQ = - 0.45 A IQ = - 0.7 A VS = VQ = 40 V IQ = 0.45 A IQ = 0.7 A
Semiconductor Group
7
1998-02-01
TLE 4729 G
Characteristics (cont'd)
VS = 6 to 16 V; Tj = - 40 to 130 C
Parameter Symbol Limit Values min. Diode Transistor Source Pair (T11, D11; T12, D12; T21, D21; T22, D22) Saturation voltage Saturation voltage Saturation voltage Saturation voltage Reverse current Forward voltage Forward voltage Diode leakage current typ. max. Unit Test Condition
VsatuC VsatuD VsatuC VsatuD IRu VFu VFu ISL
0.6 0.1 0.7 0.2 400 0.7 0.8 0
1 0.3 1.2 0.5 800 1 1.1 3
1.2 0.6 1.5 0.8 1200 1.3 1.4 10
V V V V A V V mA
IQ = 0.45 A;
charge IQ = 0.45 A; discharge IQ = 0.7 A; charge IQ = 0.7 A; discharge VS = 40 V, VQ = 0 V IQ = - 0.45 A IQ = - 0.7 A IF = - 0.7 A
Error Output Timing Time Phase X to IXX Time IXX to Phase X Delay Phase X to Error 2 Delay Phase X to Error 1 Delay IXX to Error 2 Reset delay after Phase X Reset delay after IXX
tPI tIP tPEsc tPEol tIEsc tRP tRI
- - - - - - -
5 12 45 15 30 3 1
20 100 100 50 80 10 5
s s s s s s s
For details see next four pages. These parameters are not 100% tested in production, but guaranteed by design.
Semiconductor Group
8
1998-02-01
TLE 4729 G
Diagrams Timing between IXX and Phase X to prevent setting the error flag Operating conditions: + VS = 14 V, Tj = 25 C, Ierr = 1 mA, load = 3.3 mH, 1
a) If
tPI < typ. 5 s, an error "open load" will be set.
XX
Phase X
t PI
AET02197
Figure 3
b) If
tIP < typ. 12 s, an error "open load" will be set.
XX
Phase X
t IP
AET02198
Figure 4
Semiconductor Group
9
1998-02-01
TLE 4729 G
This time strongly depends on + VS and inductivity of the load, see diagram below.
AED02199
30
t IP
s
25
VS= 6 V
20
15
10 9V 12 V 16 V
5
0 0 10 20 30 40 mH L 60
Figure 5
Time tIP versus Load Inductivity
Propagation Delay of the Error Flag Operating conditions: + VS = 14 V, Tj = 25 C, Ierr = 1 mA, load = 3.3 mH, 1 a) IXX = H, error condition: short circuit to GND.
Phase X
Error 2
t PEsc
AED02200
typ. tPEsc: 45 s
Figure 6
Semiconductor Group
10
1998-02-01
TLE 4729 G
b) IXX = H, error condition: open load (equivalent: short circuit to + VS).
Phase X
Error 1
t PEol
AET02201
typ. tPEol: 15 s
Figure 7 c) Phase X = H or L, const.; error condition: short circuit to GND.
XX
Error 2
t IEsc
AET02202
tIEsc is also measured under the condition: begin of short circuit to GND till error flag set.
Figure 8
typ. tIEsc: 30 s
Semiconductor Group
11
1998-02-01
TLE 4729 G
d) IXX = H, reset of error flag when error condition is not true.
Phase x
Error X
t RP
AET02203
typ. tRP: 3 s
Figure 9 e) Phase X = H or L, const.; reset of error flag when error condition is not true.
XX
Error X
t RI
AET02204
typ. tRI: 1 s
Figure 10
Semiconductor Group
12
1998-02-01
TLE 4729 G
Quiescent Current IS versus Supply Voltage VS; bridges not chopping; Tj = 25 C
60
AED02205
Quiesc. Current IS versus Junct. Temp. Tj; bridges not chopping, VS = 14 V
60
AED02206
S
mA 50
QX =
0.70 A
S
mA 50
QX = 0.70 A
0.45 A
40
0.45 A 0.07 A
40 0.07 A 30
30
20
20
10
10
0 5 10 15 V 20
0 -50
0
50
VS
100 C 150 Tj
Oscillator Frequency fOsc versus Junction Temperature Tj
30 kHz f Osc 25
AED02207
Output Current IQX versus Junction Temperature Tj
800 mA 700 600 500
AED02208
QX
X1 = H, X0 = H
VS = 14 V C OSC = 2.2 nF
20
400 300 200 100
X1 = H, X0 = L
V S = 14 V R X = 1
15 -50
0
50
100 C 150 Tj
0 -50
0
50
100 C 150 Tj
Semiconductor Group
13
1998-02-01
TLE 4729 G
Output Saturation Voltages Vsat versus Output Current IQ
2.0
AED02209
Forward Current IF of Free-Wheeling Diodes versus Forward Voltages VF
V sat
V 1.5
V S = 14 V T j = 25 C
F
1.0 A 0.8
AED02210
V Fl T j = 25 C
V Fu
1.0
V satuC
0.6
0.4
0.5
V satl V satuD
0.2
0
0
0.2
0.4
0.6 A 0.8
0
Q
0
0.5
1.0
V
1.5
VF
Typical Power Dissipation Ptot versus Output Current IQ (non stepping)
4
AED02211
Permissible Power Dissipation Ptot versus Case Temp. TC (measured at pin 5)
16
AED02212
P tot
W 3
L phase x = 10 mH R phase x = 2 C OSC TC
= 2.2 nF = 25 C
P tot
W 12 10 8
both phases active 2
V S = 14 V
1
T jmax =
150 C 120 C
6 4 2
0
0
0.2
0.4
0.6 A 0.8
Q
0 -25
0
25
75
125 C 175 TC
Semiconductor Group
14
1998-02-01
TLE 4729 G
Input Characteristics of IXX, Phase X
40 A 20 0 -20 -40 Phase X
AED02213
Output Leakage Current
AED02214
1.2
i xx
xx
R
mA 0.8
V S = 40 V
0.4
V S = 16 V
Tj =
-60 -80 -100 -120 -6 40 C 25 C 150 C
0
-0.4
-0.8
-4
-2
0
2
4V6 V xx
0
10
20
30 V VQ
40
Quiescent Current IS versus Supply Voltage VS; inhibit mode; Tj = 25 C
250
AED02215
S
A
200
150
100
50
0
0
5
10
15 V VS
20
Semiconductor Group
15
1998-02-01
TLE 4729 G
+12V 100 nF 11 100 F
3 Microcontroller 14 24
10 2 11
Phase 1 Error 1 Error 2 TLE 4729 G
1
VS
Q11 Q12 Q21 Q22 9 12 16 13 M Stepper Motor
21
20 23 21
22 Phase 2 OSC 4 22 nF
15 R2 1
GND 10 5,6,7,8, 17,18,19,20 R1 1
AES02216
Figure 11 Application Circuit
Semiconductor Group
16
1998-02-01
TLE 4729 G
100 F
100 nF
VS
S
+V S
V satu
V Fu
V
XX, Phase X
TLE 4729 G
Error X Output
Rl Q Ru
V satl
Err
V Err V OSC
Osc
GND
R sense
V Fl
OSC
2.2 nF
SL GND
VC
Rsense
1
AES02217
Figure 12 Test Circuit
Semiconductor Group
17
1998-02-01
TLE 4729 G
full step operation accelerate mode normal mode
10 11
H L
t
H L
t
H Phase 1 L
t i acc i set
Q1
- i set - i acc
t
i acc i set
Q2
t
- i set - i acc Phase 2 H L
t
20 21
H L
t
H L
t
AED02218
Figure 13 Full Step Operation
Semiconductor Group
18
1998-02-01
TLE 4729 G
half step operation accelerate mode normal mode
10 11
H L
t
H L
t
H Phase 1 L
t i acc i set
Q1
- i set - i acc
t
i acc i set
Q2
t
- i set - i acc Phase 2 H L
t
20 21
H L
t
H L
t
AED02219
Figure 14 Half Step Operation
Semiconductor Group
19
1998-02-01
TLE 4729 G
V Osc V Osc H V Osc L
Rsense 1
0
t
Rsense 2
0
t
t V FU V satl
V Q12 + VS V ca 0 V Q11 + VS V Q22 + VS
t V satu D V satu C
0 V Q21 + VS
t
Q1
i acc
Q2
i acc
t
t
Operating conditions:
VS = 14 V L phase x = 10 mH R phase x = 4
Phase x = H =H XX
AED02220
Figure 15 Current Control in Chop-Mode
Semiconductor Group
20
1998-02-01
TLE 4729 G
V Osc 2.3 V
1.3 V 0V Phase H L Oscillator High Imped. Phase change-over
t t
Rsense 1
0
t
V Q11
+V S High Impedance
t V Q12
+VS High Impedance
t
Phase 1
set
fast current decay
T1
slow current decay - set slow current decay
t
Operating conditions:
VS = 14 V L phase 1 = 1 mH R phase 1 = 4
11 = L for t < T 1 11 = H for t > T 1 10 = 2X = L
AED02221
Figure 16 Phase Reversal and Inhibit
Semiconductor Group
21
1998-02-01
TLE 4729 G
Calculation of Power Dissipation The total power dissipation Ptot is made up of (transistor saturation voltage and diode forward saturation losses Psat voltages), (quiescent current times supply voltage) and quiescent losses Pq (turn-ON / turn-OFF operations). switching losses Ps The following equations give the power dissipation for chopper operation without phase reversal. This is the worst case, because full current flows for the entire time and switching losses occur in addition.
Ptot = 2 x Psat + Pq + 2 x Ps
where
Psat IN {VsatI x d + VFu (1 - d) + VsatuC x d + VsatuD (1 - d)} Pq = Iq x VS V S i D x t DON ( i D + i R ) x t ON I N P q ----- -------------------- + --------------------------------- + ---- ( t DOFF + t OFF ) T 2 2 4
IN Iq iD iR tp tON tOFF tDON tDOFF T d Vsatl VsatuC VsatuD VFu VS
= nominal current (mean value) = quiescent current = reverse current during turn-on delay = peak reverse current = conducting time of chopper transistor = turn-ON time = turn-OFF time = turn-ON delay = turn-OFF delay = cycle duration = duty cycle tp / T = saturation voltage of sink transistor (TX3, TX4) = saturation voltage of source transistor (TX1, TX2) during charge cycle = saturation voltage of source transistor (TX1, TX2) during discharge cycle = forward voltage of free-wheeling diode (DX1, DX2) = supply voltage
Semiconductor Group
22
1998-02-01
TLE 4729 G
+V S
Tx1
Dx1
Dx2
Tx2
L
Tx4
Tx3
Dx3
Dx4
VC R sense
AET02222
Figure 17
Turn-ON Voltage and Current on Chopper Transistor
Turn-OFF
iR iD
N
V S + V Fu
V S + V Fu V satl t D ON t ON tP t D OFF t OFF t
AET02223
Figure 18 Voltage and Current on Chopper Transistor
Semiconductor Group
23
1998-02-01
TLE 4729 G
Application Hints The TLE 4729 G is intended to drive both phases of a stepper motor. Special care has been taken to provide high efficiency, robustness and to minimize external components. Power Supply The TLE 4729 G will work with supply voltages ranging from 5 V to 16 V at pin VS. Surges exceeding 16 V at V S wont harm the circuit up to 45 V, but whole function is not guaranteed. As soon as the voltage drops below approximately 16 V the TLE 4729 G works promptly again. As the circuit operates with chopper regulation of the current, interference generation problems can arise in some applications. Therefore the power supply should be decoupled by a 0.1 F ceramic capacitor located near the package. Unstabilized supplies may even afford higher capacities. Inhibit Mode In the case of low at all four current program inputs IXX the device will switch into inhibit condition; the current consumption is reduced to very low values. When starting operation again, i.e. putting at least one IXX to high potential, the Error 1 output signals an open load error if the corresponding phase input is high. The error is reset by first recirculation in chop mode. Current Sensing The current in the windings of the stepper motor is sensed by the voltage drop across Rsense. Depending on the selected current internal comparators will turn off the sink transistor as soon as the voltage drop reaches certain thresholds (typical 0 V, 0.07 V, 0.45 V and 0.7 V). These thresholds are not affected by variations of VS. Consequently instabilized supplies will not affect the performance of the regulation. For precise current level it must be considered, that internal bounding wire (typ. 60 m) is a part of Rsense. Due to chopper control fast current rises (up to 10 A/s) will occur at the sensing resistors. To prevent malfunction of the current sensing mechanism Rsense should be pure ohmic. The resistors should be wired to GND as directly as possible. Capacitive loads such as long cables (with high wire to wire capacity) to the motor should be avoided for the same reason. Synchronizing Several Choppers In some applications synchrone chopping of several stepper motor drivers may be desirable to reduce acoustic interference. This can be done by forcing the oscillator of the TLE 4729 G by a pulse generator overdriving the oscillator loading currents (approximately 120 A). In these applications low level should be between 0 V and 0.8 V while high level should between 3 V and 5 V.
Semiconductor Group 24 1998-02-01
TLE 4729 G
Application Hints (cont'd) Optimizing Noise Immunity Unused inputs should always be wired to proper voltage levels in order to obtain highest possible noise immunity. To prevent crossconduction of the output stages the TLE 4729 G uses a special break before make timing of the power transistors. This timing circuit can be triggered by short glitches (some hundred nanoseconds) at the phase inputs causing the output stage to become high resistive during some microseconds. This will lead to a fast current decay during that time. To achieve maximum current accuracy such glitches at the phase inputs should be avoided by proper control signals. To lower EMI a ceramic capacitor of max. 3 nF is advisable from each output to GND. Thermal Shut Down To protect the circuit against thermal destruction, thermal shut down has been implemented. Error Monitoring The error outputs signal corresponding to the logic table the errors described below. Logic Table Kind of Error Error 1 a) No error b) Short circuit to GND c) Open load 1) d) b) and c) simultaneously e) Temperature prealarm
1)
Error Output Error 2 H L H L L H H L H L
Also possible: short circuit to + VS or short circuit of the load.
Over-Temperature is implemented as pre-alarm; it appears approximately 20 K before thermal shut down. To detect an open load, the recirculation of the inductive load is watched. If there is no recirculation after a phase change-over, an internal error flipflop is set. Because in most kinds of short circuits there won't flow any current through the motor, there will be no recirculation after a phase change-over, and the error flipflop for open load will be set, too. Additionally an open load error is signaled after a phase change-over during hold mode.
Semiconductor Group
25
1998-02-01
TLE 4729 G
Only in the case of a short circuit to GND, the most probably kind of a short circuit in automotive applications, the malfunction is signaled dominant (see d) in logic table) by a separate error flag. Simultaneously the output current is disabled after 30 s to prevent disturbances. A phase change-over or putting both current control inputs of the affected bridge on low potential resets the error flipflop. Being a separate flipflop for every bridge, the error can be located in easy way.
Semiconductor Group
26
1998-02-01
TLE 4729 G
Package Outlines P-DSO-24-3 (Plastic Dual Small Outline Package)
2.65 max
0.35 x 45
+0.09
2.45 -0.2
0.2 -0.1
7.6 -0.2 1)
1.27 0.35 +0.15 2) 24 0.2 24x 13 0.1
0.4 +0.8 10.3 0.3
1 Index Marking
15.6 -0.4 1)
12
1) Does not include plastic or metal protrusions of 0.15 max rer side 2) Does not include dambar protrusion of 0.05 max per side
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Dimensions in mm
Semiconductor Group
27
0.23
GPS05144
8 ma
x
1998-02-01

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